(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for polishing copper surfaces by using electropolish without thereby incurring negative effects of low-k dielectric peeling and surface dishing.
(2) Description of the Prior Art
A significant aspect of the creation of semiconductor devices addresses the interconnection of these devices. For these interconnections, metals such as aluminum or their alloys have been used extensively in the past. In more recent developments copper is becoming the preferred material for the creation of metal interconnects. Copper has of late been the material of choice in view of the more attractive performance characteristics of copper such as low cost and low resistivity. Copper however has a relatively large diffusion coefficient into surrounding dielectrics such as silicon dioxide and silicon. Copper that forms a conductive interconnect may diffuse into the surrounding dielectric, causing the dielectric to be conductive and decreasing the dielectric strength of the silicon dioxide layer.
Copper interconnects are therefore preferably encapsulated by at least one diffusion barrier to prevent diffusion into the surrounding dielectric layer. Silicon nitride is a diffusion barrier to copper, but the prior art teaches that the interconnects should not lie on a silicon nitride layer because it has a high dielectric constant compared with silicon dioxide. The high dielectric constant causes an undesired increase in capacitance between interconnects and the substrate. Copper further has low adhesive strength to various insulating layers, while it has been proven inherently difficult to mask and etch a blanket copper layer into intricate circuit structures.
While copper has become important for the creation of multilevel interconnections, copper lines frequently show damage after Chemical Mechanical Polishing (CMP) and clean. This in turn causes problems with planarization of subsequent layers that are deposited over the copper lines, since these layers may now be deposited on a surface of poor planarity. Isolated copper lines or copper lines that are adjacent to open fields are susceptible to damage. Poor copper gap fill together with subsequent problems of etching and planarization are suspected as the root causes for these damages. Where over-polish is required, the problem of damaged copper lines becomes even more severe.
The increasing need to form planar surfaces in semiconductor device fabrication has led to the development of a process technology known as Chemical Mechanical Planarization (CMP). In the CMP process, semiconductor substrates are rotated, face down, against a polishing pad in the presence of abrasive slurry. Most commonly, the layer to be planarized is an electrical insulating layer overlaying active circuit devices. As the substrate is rotated against the polishing pad, the abrasive force grinds away the surface of the insulating layer. Additionally, chemical compounds within the slurry undergo a chemical reaction with the components of the insulating layer to enhance the rate of removal. By carefully selecting the chemical components of the slurry, the polishing process can be made more selective to one type of material than to another. For example, in the presence of potassium hydroxide, silicon dioxide is removed at a faster rate than silicon nitride. The ability to control the selectivity of a CMP process has led to its increased use in the fabrication of complex integrated circuits.
Conventional methods of Chemical Mechanical Polishing (CMP) are known to cause problems of peeling of the surrounding low-k dielectric and of dishing and corrosion of the polished copper surface. As an alternative to CMP, the process of electropolish is gaining increased acceptance. Polishing results that are obtained by applying electropolish however are affected by a density effect, whereby isolated lines are stripped at a much higher rate due to the higher current density carried by the isolated lines. The invention addresses these issues.
U.S. Pat. No. 5,091,339 (Carey) shows a copper removal process.
U.S. Pat. No. 6,319,384 B1 (Taylor et al.) shows a pulse reverse electro deposition process.
U.S. Pat. No. 6,329,324 (Ma et al.) shows a copper etchback planarization process.
U.S. Pat. No. 6,107,186 (Erb) shows a copper planarization process.